The present invention relates generally to circuit output drivers and in particular the present invention relates to a circuit for controlling slew rates.
Integrated circuits can be provided to communicate data over a communication bus. The integrated circuits include both a data transmitter, or driver circuit, and a receiver circuit. Communicating data signals on the communication bus can be complicated and is the subject of extensive studies relating to transmission lines. To reduce data signal ringing and signal interference, the rise time or slew rate of a signal transmitted on the data bus is often controlled. In addition, an impedance mismatch between the integrated circuit driver and the communication bus can increase the signal ringing and interference. As such, it is common to employ techniques to reduce impedance mismatch.
In addition to controlling data communication slew rate and driver circuit impedance matching, a reduction in the communication bus lines is desired. That is, two data lines can be provided between integrated circuits. One data line communicates in a first direction, while the second data line is used for data communication in an opposite second direction. It is desired to reduce the two data lines by using a single data communication line. By using a single data line which communicates data in two directions simultaneously, signal interference between the two data signals creates additional difficulties in reliable data communication. As such, reference circuitry can be used to subtract a data signal, which is being transmitted, from the data signal received to isolate the received data.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a bidirectional data communication circuit which can provide slew rate control on transmitted data and maintain adequate noise margin on received data signals.
In one embodiment, a data communication circuit comprises a delay line circuit coupled to receive an output data signal. The delay line circuit includes a plurality of output connections for providing the output data signal, where a signal provided on each of the plurality of output connections is delayed from a previous one of the plurality of output connections. A data driver circuit is provided which comprises a plurality of stage circuits coupled to the plurality of output connections of the delay line circuit such that a slew rate of a data signal transmitted by the data driver circuit can be controlled by the delay line circuit. A data receiver circuit is coupled to the delay line circuit. A slew rate of a reference voltage signal coupled to the data receiver circuit can be controlled by the delay line circuit such that the slew rate of the data signal transmitted by the data driver circuit and the slew rate of a reference voltage signal are substantially the same.
In another embodiment, an integrated circuit is provided which comprises an output connection which can be coupled to an external data communication line, and a delay circuit having an input connection for receiving a data signal and a propagation path comprising a plurality of delay circuits. The delay circuit has a plurality of output connections located along the propagation path to provide digital output signals in response to the received data signal. A data driver circuit is coupled to the output connection and the plurality of output connections of the delay circuit. The data driver circuit comprises a plurality of stage circuits which can be selectively activated by the digital output signals to control a slew rate of an output data signal coupled to the output connection and maintain a constant impedance at the output connection while the data signal is transmitted. A data receiver circuit is provided which comprises a first input coupled to the output connection, a second input coupled to receive a first reference voltage signal, and a third input coupled to receive a second reference voltage signal. The data receiver circuit further comprises slew rate control circuitry coupled to the plurality of output connections of the delay circuit to control a slew rate of a trip point between the first and second reference voltage signals.